(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a new design of a die “oxide ring” and a method for the fabrication of this oxide ring.
(2) Description of the Prior Art
Cost-competitive pressures require that semiconductor devices are created at a minimum cost, which results in numerous semiconductor devices simultaneously being created over a substrate.
After the semiconductor devices have been created over a substrate, independent operational units, also known as semiconductor die, are created by singulating or separating the substrate into individual units. This latter process is known as die dicing, a process that is frequently performed by sawing the die along die sawing paths that have for this purpose been provided between and surrounding the individual semiconductor die.
Since a sawing process tends to be a rather abrasive process, it is to be expected that the process is prone to cause die failures and can therefore be a leading yield detractor.
Increased performance of semiconductor devices is in more advanced semiconductor devices among others achieved by incorporating low-k dielectric as insulating materials and copper as interconnect metal into the design and creation of the semiconductor devices.
Low-k dielectric materials present a challenge in view of their high porosity, which leads to easy absorption of moisture by the low-k dielectric, and their low internal stress tolerance, which leads to cracking or the development of fissures if mechanical stress is exerted on the low-k dielectric.
It can readily be expected that, in singulating semiconductor die into individual units, the low-k dielectric is most prone to disruptions, such as cracking, in the corners of the singulated die which are formed by intersections of the sawing paths. The cracking, which originates in the corners of the singulated die, readily extends from the corners across the surface of the die, which in turn leads to potentially placing stress on and even interrupting conductive interconnects, comprising for instance copper, that form part of the singulated die.
In view of the complexity of a high-performance semiconductor die and the there-with associated complexity of the elements that constitute the semiconductor die, a detailed stress analysis for improved understanding of the cracking of low-k dielectric is not readily achieved.
A number of observations can however be made that point towards reasons for the cracking of the low-k dielectric and the thereby introduced negative impact on the complete package of the die.
In a modern, high-performance semiconductor die, it is not uncommon to encounter between 6 and 8 interspersed layers of copper and Inter Metal Dielectric (IMD), thereby including for instance two layers of oxides overlying layers of low-k dielectric. Die passivation is achieved by the deposition of 2 or 3 layers of passivation, thereby including layers of silicon nitride and Undoped Silicon Glass (USG). Brittle, low-k dielectric has a high propensity to crack when subjected to mechanical stress.
It has further been observed that dicing induced cracking most readily occurs when the sawing blade enters the interface between soft but tough copper and hard but brittle CVD low-k dielectric material. It is to be expected that, at these interfaces, the cutting speed may change drastically due to the very different mechanical properties of these materials.
This drastic change in cutting speed readily causes dragging and peeling of the relatively hard but brittle low-k dielectric material. At the time that the sawing blade cuts through the copper interconnect, the copper interconnect may not immediately be cut (and break apart) due to the high tensile toughness of the copper.
It is in this scenario reasonable to expect that the copper, at the time that the copper is being cut, exerts a mechanical force or pull on the surrounding low-k dielectric, thereby moving or deforming the surrounding low-k dielectric. In view of the fact that the low-k dielectrics, which are frequently used for high-performance, advanced semiconductor devices, comprise CVD oxides which are relatively brittle, it stands to reason that peeling, along different dielectrics and along dielectric to copper interfaces, and cracking of the low-k dielectrics is difficult to avoid when singulating a substrate into individual die. This peeling and cracking has been observed, as previously stated, to be most prominent at corners of the singulated die, where the X and Y directions of the sawing paths intersect.
The invention addresses the above highlighted concerns of damage introduced to a semiconductor die by the process of die singulation.
U.S. Pat. No. 5,776,826 (Mitwalsky et al.) describes a fuse etch to form a crack stop to prevent cracks from propagating during dicing.
U.S. Pat. No. 6,509,622 (Ma et al.) discloses a plurality of metal guard rings to prevent cracks.
U.S. Pat. No. 6,596,562 (Maiz) teaches using a laser gun to form trenches between guard rings to isolate the saw from the integrated circuits.
U.S. Pat. No. 6,107,161 (Kitaguro et al.) shows forming cutting grooves outside of the guard ring to prevent cracking during dicing.